Digital frequency filter and function generator



A ril 2, 1968 Filed Dec. 13, 1963 M. PRAGER DIGITAL FREQUENCY FILTER ANDFUNCTION GENERATOR 5 Sheets-Sheet 1 32 3e PIN 45 37 38 (42 q46 22 49 I IP s [28 r52 1 l V OUT R3 39 \DELAY LINE SCALER SCALER) 4 {CLOCK 40 F I6.I

WAVE 42 SET-- f SCALER) SHAK/ER RESET-/ IO4 LDELAY LINE 1 .4 SYNC": IOZF SCALER' F IG. 6

- INVENTOR. MELVIN PRAGER RmS} Sam ATTORNEYS April 2, 1968 M. PRAGER 3,

DIGITAL FREQUENCY FILTER AND FUNCTION GENERATOR Filed Dec. 13, 1963 5Sheets-Sheet 2 INVENTOR. MELVIN PRAGER ROMQ SM".

ATTORNEYS NUMBER OF PULSES N MEMORY M. PRAGER April 2, 1968 5Sheets-Sheet 3 Filed Dec. 13, 1963 POUT m E w A /|L W [k v E 6 R m E M4. O E 6 4 m 6 L 2 Y 6 A a E Q J 5 2 m s E G w M K Cl 4 C w m 6 C 3 m LO 8 m 4 4 S M N 4 O n 8 8 u 7 N 6 2 I Y 7 R C F. D 4 S 7 m 6 O 8 u SWEEPRETRACE o h" d TIME F IG. 4

INVENTOR.

MELVIN PRAGER ROMS;

ATTORNEYS United States Patent 19 Claims. or. 235-165) This applicationis a continuation-in-part of Ser. No. 299,745, Aug. 5, 1963.

This invention relates to frequency function generation, andparticularly to the generation of frequency func tions by digitaltechniques.

Devices capable of performing operations on the frequency of a giveninput signal (i.e. generating an output frequency which is a function ofthe input frequency) are well known, and include devices operating oninput fre quencies of either continuous (e.g. sinusoidal type) ordiscontinuous (e.g. pulse or square wave type) periodic proc esses.Typical devices of this nature are known frequency multipliers,frequency dividers, frequency squarers, and the like, which can beconsidered static devices in that the equation of the function relatinginput to output frequencies has no differential coefiicients. Also knownare dynamic devices such as frequency modulators wherein the outputfrequency is dilferentially related to an independent variable such asthe input frequency.

The latter category of devices is usually an analog instrument, i.e. thetechniques for varying frequency as a first or higher order derivativeare not through quantized steps, and the accuracy of the relationshipbetween independent variable and output frequency is limited. Forexample, if one wishes to provide a signal generator by which an outputfrequency is determined as a linear function of a ramp voltage, thereare readily available voltageto-frequency converters of the analog typesuch as the unit described in Electronics, vol. 36, No. 17, Apr. 26,1963, pp. 64, 65. However, analog devices are often not either asflexible or as capable of inherent extension of accuracy as digitaldevices. Analog devices also reflect in their output discontinuities intheir input. For example, if, in a voltage-to-frequency converter of thetype above described, the input voltage changes from one level toanother substantially instantaneously, the output function, i.e.frequency, will abruptly and discontinuously change also.

Where one wishes to employ, for example, a stepping motor as in aplotter device, it is known that while the step-motor can be made tooperate at speeds considerably above the maximum start-stop speedrecommended if acceleration and deceleration limits are observed, themotor will not respond with accuracy to input pulse trains whoserepetition rate varies discontinuously. If one employs a pulse train asan input to a rate-multiplier device, it will be apparent that if themultiplication factor is large, sharp changes in the repetition rate ofthe pulse train will emerge from the multiplier as rate changes ofslopes so high as to be considered discontinuities. Obviously then, theoutput of such rate-multiplier devices do not appear to be appropriatefor use as stepping motor input.

A principal object of the present invention is therefore to provide adigital frequency filter which will accept as an input a periodic signaltrain which can vary discretely or discontinuously in its frequency orrepetition rate, and provide an output in which the frequency variessmoothly or continuously within the limitation imposed by digitalincrements. Other objects of the present invention are to provide such afilter comprising means for serially time-compressing binaryrepresentation, taken at a predetermined rate, of the frequency of aninput signal, and means for time-expanding the compressed binaryrepresentations so as to provide an output signal having a frequencywhich is a weighted average, over a predetermined time period, of theinput signal frequency; to provide a filter of the type describedwherein the means for serially time-compressing includes a serial datastorage device having a predetermined storage time, and the time periodover which the input frequency is averaged is determined in accordancewith the storage time of the storage device and rate at which the binaryrepresentations are taken; and to provide a basic filter system whichcan be employed in a variety of configurations as a building block inthe construction of digital frequency function generators.

Further objects of the present invention are to provide, through the useof digital techniques, systems for generating frequency functions, whichare capable of high stability, accuracy and flexibility of performance;to provide such systems, employing time-compression techniques, togenerate periodic output signals whose frequency or repetition rate isrelated to an input or base signal frequency linearly, exponentially orthe like; and to provide such systems wherein time-compression isbasically achieved by the selective gating of feedback signals from theoutput to the input of a serial memory or signal storage device.

Other objects of the invention will in part be obvious and will in partappear hereinafter. The invention accordingly comprises the apparatuspossessing the construction, combination of elements, and arrangement ofparts which are exemplified in the following detailed disclosure, andthe scope of the application of which will be indicated in the claims.For a fuller understanding of the nature and objects of the presentinvention, reference should be had to the following detailed descriptiontaken in connection with the accompanying drawings wherein:

FIG. 1 is a block logic diagram of an embodiment of the presentinvention which provides a digital filter;

FIG. 2 is a timing diagram showing the relation of the pulses at variouspoints in the embodiment of FIG. 1. during operation thereof;

FIG. 3 is a block logic diagram of the digital filter system employed toform another embodiment of the present invention to provide a linear F Msignal generator;

FIG. 4 is a frequency-time plot showing a typical ide-. alized waveformof the output of the embodiment of. FIG. 3;

FIG. 5 is a frequency time plot showing detailed frequency variation ofan expanded portion of the plot of FIG. 4 indicated on the latter atbroken circle 5; and

FIG. 6 is'a block logic diagram of the digital filter system employed toform yet another embodiment of the present invention to provide anexponential FM signal output.

In effecting the foregoing objects, the present invention employs anovel digital delay-line time-compression technique. Certaintime-compression techniques are known in the digital arts and have been,in a form known as a Deltic loop, described in detail by Rosenbloom,Electronics, Mar. 10, 1961, and by V. C. Anderson, Technical MemorandumNo. 37 (NR-014-903) Harvard Univ., Acoustics Laboratory, J an. 5, 1956.The Deltic loop samples the amplitude of a variable amplitude inputsignfl and time-compresses the amplitude envelope such that the outputsignal, while having substantially the same amplitude information as theinput signal, is at a considerably higher frequency. Thus, long termchanges in amplitude are time-compressed and through the use of theDeltic loop in signal correlation equipment, a large number of amplitudecorrelations can be realized in reduced real-time. Additionally, theDeltic loop has found 3 application in spectral analysis of lowfrequency phenomena.

Generally, and in contrast to the Deltic loop, a digital filter of thepresent invention is adapted to accept a pulse train representative of abase frequency only, rather than of amplitude. For example, if a basesignal is sinusoidal, its frequency can be digitized by insertion of thesignal into an axis-crossing detector. The output pulse train of thedetector then contains information relating only to input frequency, allinformation relating to the magnitude and sense of amplitude beingdiscarded.

Means are provided for time-compressing the frequency information, andto this end there is included a selective gating system which, ineffect, holds for sampling and then samples, in accordance with samplingsignals, the input pulse train, and synchronously inserts the samplingsinto the input of a serial data storage or memory device. The samplingsare stored in the memory for a predetermined time period and arepresented seriatim at an output terminal. Means are also provided forconnecting and disconnecting a feedback loop from the output terminal tothe input of the memory device in accordance with the presence or lackthereof of a sampling signal. Alternatively, rather than employingsampling signals to inhibit (or enable as the case may be) feedback, thefeedback itself may be employed to provide inhibition or enablement ofthe sampling signals. The time-compression achieved in the memory is ofthe frequency information. The time-compressed pulses are thentime-expanded by appropriate means so that the frequency or repetitionrate of the output signal of the filter is then a multiple orsub-multiple of a time-average of the original input frequency. Withappropriate choice of parameters, the frequency gain of the filter canbe made unity, or any other arbitrary rational number, for static orquasi-static conditions of input frequency. Unlike other frequencychangers, such as harmonic generators, static input and outputrepetition rates of the filter are related according to a ratio of twoscaling divisors which then in decimal notation can be either arepetitive or a terminating rational number and is not limited to wholenumbers. However, when the input frequency conditions are dynamic ordiscontinuous, the filter does not provide a correspondingdiscontinuity, but acts, somewhat in the manner of an integratingoperational amplifier, to reflect a discontinuous or step inputfrequency change as a continuous or ramp-like output frequency change.

For example, referring now to FIG. 1, there will be seen an embodimentof the filter of the present invention including means for sampling therepetition rate of an input pulse train P Such means is shown ascomprising flip-flop 20 having set and reset terminals 22 and 24respectively. One of terminals 22 and 24 is adapted for connection tothe source of P the other of the terminals being connected to the outputof a two-input-terminal coincidence or AND gate 26. Flip-flop 20 alsohas an output terminal 28 at which a signal will or will not appeardepending upon the selective excitation of the set and reset terminals.The embodiment of FIG. 1 also includes a pair of two-input terminalcoincidence or AND gates 32 and 34 having their respective outputterminals buffered together at the input of OR gate 36. The output ofgate 36 is coupled to one input terminal 37 of another two-input ANDgate 38, the other input terminal 39 of gate 38 being connected to asource of timing pulses, such as clock 40. The output of gate 38 isconnected to the input of a serial memory, such as delay line 42. Theoutput of delay line 42 is connected via a feedback loop 44 to one input45 of gate 42 and is also connected to the input of first frequencydivider or sealer 46.

Clock 40 is also connected to the input of second frequency divider orsealer 48, the output of the latter being connected to inhibiting inputterminal 49 of gate 32, to enabling input terminal 50 of gate 34, and toenabling input terminal 51 of gate 26. Connected to output terwhere R isdefined as the compression ratio and is the integral divisor provided bysealer 48. The latter, as is well known in the art, can typically be amultistage chain of multivibrators or flip-flops providing an ultimateoutput frequency (F in this example) which is an integral, sub-multipleof its input frequency (e.g. F

Hence, enabling input terminals 50 and 51 of gates 34 and 26respectively, and inhibiting input terminal49 of gate 32, are allsimultaneously periodically energized at a rate F Gates 26, 32, 34, 36and 38 can be typical transistor gates, diode gates or the like,according to the needs of the designer as is well known in the art. F isat least equal to or greater than the maximum expected repetition rate,F of the input signal P The input pulse train P is typically derived, ashereinbefore explained, from a bipolar axis-crossing detector. Hence,each pulse of P will energize set terminal 22, providing an output onterminal 28 which will persist, for example, as a fixed DC level, untilreset terminal 24 is energized. If there is a signal at terminal 28, itwill also appear at terminals 52 and 53 of gates 34 and 26.. Whenterminals 50 and :51 are simultaneously energized by a sampling pulse,both gates 34 and 26 will provide output pulses. The pulse from gate 26then resets flip-flop 20 and the output on terminal 28 disappears, toreappear at the time of the next pulse in the train P Referring now toFIG. 2, there will be seen representations of certain exemplary graphs,all on the same horizontal time axis in microseconds. The first plot,labeled P is a pulse form of the input signal. Two pulse waveformslabeled P and P are respectively the pulse trains of frequencies F and FFor the sake of exposition, arbitrary values can be assumed indescribing the plots of FIG. 2. For example, it can be assumed that theexcursion of P is between zero repetition rate F and an arbitraryrepetition rate of magnitude F and occurs substantially instantaneously.The clock pulse train P for example, can be considered as having a 1 me.repetition rate (readily attained typically from knowncrystal-controlled pulses oscillators or the like), the pulses thusbeing separated by 1 ,usec, intervals and having a pulse width of muchless than 1 ,usec. If R is taken at an exemplary value of 8, then thepulses in the sampling train P are separated, as shown, by 8 nsec.intervals. The period of F pulses is also shown as 8 asec solely for thesake of simplicity.

If, as shown, the first sampling pulse of interest occurs at t thesecond at t the third at r then the nth pulse will occur at tRcc(n 1)where t to 1 is the basic period set by the clock pulse train. Assumingflip-flop 20 to be in its reset condition, because the excursion of Pfrom F to F does not occur until after t there is no output on terminal28 of the flip-flop, and the enabling of gate 34 by the sampling pulseat t does not create any output from gate 34. However, when gate 34 isnextenabled at 1 by the second sampling pulse, because a pulse of P hasset flip-flop 20 and thus energized terminal 52 at t an output firstsampled pulse is provided by gate 34 through OR gate 36 to inputterminal 37 of gate 38.

The simultaneous inputs also occurring at terminals 53 and 51 of gate 26energize reset terminal 24 of the flipfiop, restoring the latter in itsreset condition. It will be appreciated that some small delay isdesirable so that the flip-flop does not reset until the output pulsefrom gate 34 has occurred. Gate 38 is placed in enabled con dition bythe pressure at its other input terminal 39 of a clock pulse from clock40 appearing at t so that the first sample pulse is passed into delayline 42 which then operates as a serial memory. The delay line may beany appropriate storage device operated serially such as a shiftregister, magnetic drum, tape loop, core buffer storage, and the like,but is most simply and preferably a magnetostrictive delay line of knowntype. If the delay of line 42 is T expressed for example in usecs, thememory capacity M in bits (signal pulses i.e. ONES, or lack thereof,i.e. ZEROS) of the line can be defined as If the memory delay T shouldbe selected to be, for example, one ,usec. (i.e. a clock pulse interval)shorter than the period between sampling pulses, the sampled pulsesinserted into the delay line at reappears at an input or recirculationterminal 45 of gate 32 l ,usee (as shown on the diagram of FIG. 2 markedP before I' the time of the next successive sampling pulse. Gate 32,being uninhibited at 13 thus applies the sampled pulse through OR gate36 to coincidence gate 38 where the appearance of the enabling clockpulse at 1' allows the sampled pulse to. be reinserted into the delayline. The clock pulses, enabling gate 38, thereby provide precise timingfor pulse reinsertion. One microsecond later, at m, gate 32 is inhibitedand gate 34 is enabled by the third sampling pulse in train P As theoutput of flipfiop Z0 is energizing terminal 52 at 1 a second sampledpulse is therefore inserted into the delay line, trailing the firstsampled pulse by only 1 ,usec. In a similar manner, subsequent bitstaken at 8 ,nsecond intervals, either as ONES or ZEROS due to the natureof the output of flip-flop 2G existing at the time gate 34 is enabled,are inserted and reinserted in the delay line until the latter contain Mbits separate by 1 sec. intervals. Where, as in FIG. 2 T has "beenchosen to be 7 ,usec. and F is 1 mc., then M=7. It should be emphasizedthat these values are set forth here solely for the sake of clarity inexposition. It will also be appreciated that the input pulses can bequite random, provided that F is equal to or greater than the maximum Pand, in some instances, additional synchronizing stages or flipflops areprovided.

It will be apparent that, although in the example given here, P goes tothe F level from F substantially instantaneously, the transition of theF frequency to the digital number representing the F frequency requiresa finite time, T which is realted as follows:

In the portion of FIG. 3 wherein the number of pulses stored in thedelay line are plotted against the time axis, it will be seen that thedigital representation (number of bits) of the frequency of P varies intime in discrete uniform increments or steps forming a staircase or rampwhich indicates the smooth digital transition during T of adiscontinuous analog value change occurring immediately prior to thebeginning of period T Hence T is the time constant of the system.

When delay line 42 becomes full, the first inserted sampled pulse willarrive at recirculation input 45 of gate 32 simultaneously with theoccurrence of a sampling pulse from compressor 48. This is shown in FIG.2 as occurring at r Because gate 32 is then inhibited by that samplingpulse, the first inserted sampled pulse is discarded; however,simultaneously, gate 34 is enabled so that the output thereof, either asa pulse (ONE) or no pulse (ZERO), is inserted into the delay line. Itwill be apparent that the content of the delay line is then beingcontinually revised or updated as the older data is simultaneoulydiscarded.

Because the delay line will contain digital information in the form of Mbits separated by 1 sec. clock intervals (according to this example),the M bits being reprefit sentative of analog information occurring overa period of time approximately MxR ,usec, the information in the delayline can be considered time-compressed.

The output of the delay line is also connected to the input of scaler46, such as a frequency divider of known type formed for example as isscaler 48. The output is therefore, on passage through scaler 46,time-expanded to provide a given output frequency. For the steady orstatic state of F the output frequency F of the scaler is related to Fi.e.

F OUT=%'F IN For the changing or dynamic state of F the precedingEquation 4 is equally valid if it is then understood that F refers to anaverage value of F over a period of time. If the divisor Y provided byscaler 46 is equal to R the static frequency gain is unity.

Referring again to FIG. 2, it will be seen that, by a reverse process ofstorage of ZEROS rather than ONES, the delay line can be considered todump its memory upon reversion of the input signal P from its F level toits F level. And even if this reversion is substantially instantaneous,the dumping of the memory requires a finite time, i.e. T which hasalready been defined. Thus, the discontinuous change in inputfrequencies of P are smoothed or filtered by the present invention toprovide the symmetrical representation marked P indicating that thediscontinuities of P within the limits of quantized steps, have beensmoothed with a delay or integration time constant of T or expressed inanother manner, have been averaged over a period (T of time. Theaveraging, of course, is weighted by the gain, i.e. the ratio R Y. Ineffect, the filter of FIG. 1 within the time constant acts somewhat asan integrator in that a step input of frequency produces a linear changein frequency at the output. In a more general sense, the filter providesan output frequency which is the time-average of the input frequency.Hence, it can serve as a matching filter, for example, to a step-motorin a position control system. By doing so, it is possible to achieveapproximately an order of magnitude improvement in motor speed withoutsacrifice in accuracy.

The nature of scaler 46, which is in effect a counter, will under somecircumstances, create a dissymmetry between the beginning (i.e. around 2and the ending (i.e. around t time rates of frequency change in Palthough the pulse trains representative of these rates appearsymmetrically at the output of the delay line. In effect, this is a skewdue to phase shift introduced by the scaler. To a large measure, thisdissymmetry can be minimized, if desired, by having scaler 46 presetwith a count of approximately Y/2. Thus, P shown is based upon a Y of 8for scaler 46, the latter being preset with a count of 4. It is ofinterest that where R =Y and the frequency gain is therefore unity,counter or scaler 46 will continue to remain preset with the originalcount of Y/2, i.e. the phase shift remains constant.

Because the digital filter system of FIG. 1 provides an extremely stabletime-variant frequency function which can, depending for example on theextent of the timecompression, be achieved with a high order ofaccuracy, the substance of the digital filter system can be used in theformation of digital generators of various time functions of frequency.For example, one can thus generate a wave-train whose frequency variesas a function (for example linearly) of time between two frequencylimits, F and F A typical function of this type is where t is a fixedsweep time interval and k is any arbitrary number. Thus, if F is 3.3ice, I varies from O to 0.5 second and k=800, the generated outputwaveform will exhibit a linear frequency change from 3.3 to 3.7 kc. overa 0.5 second interval.

This can be achieved broadly by providing a fixed frequency signal asone limit, providing a time-linear frequency variation of proper scope,and literally subtracting (or adding, as the case may be) the linearfrequency variation from the fixed frequency signal. The time-linearfrequency variation is advantageously provided by a digital filtersimilar to that shown forming part of FIG. 3. As in FIG. 1, likenumerals being employed to indicate like parts, the embodiment of FIG. 3includes inhibit means such as two-legged gate 32 having recirculatinginput terminal 45 and inhibiting terminal 49. In order to beconsistentwith FIG. 1, input gate 34 is also included, but is shown asbeing single-legged, i.e. only one input terminal 52 is employed. Gate34 is therefore not, strictly speaking, a coincidence gate which canperform sampling, but does have an output whenever an input signal isapplied to terminal 52. Gate 34, as later described in detail, serves asa reset control to the time compressor. This embodiment also includes ORgate 36 which buffers together the outputs of gates 32 and 34, and whichin turn has its output connected to one input terminal 37 of AND gate38. The output of the latter is connected to the input of delay line 42.Feedback path 44 is provided for connecting the output of delay line 42with recirculating input terminal 45.

As in FIG. 1, the embodiment of FIG. 3 also includes clock 40 connectedto enabling input terminal 39 of gate 38 and also connected to the inputof a frequency divider or sealer 48. The output of the latter isconnected to inhibiting terminal 49 of gate 32. Similarly, the output ofdelay line 42 is also connected to a frequency divider or sealer 46.

Additionally, the embodiment of FIG. 3 includes subtraction means in theform of another concidence gate 60 having inhibiting input terminal 62connected to the output of the first sealer 46. Another input terminal64 is connected to the output of clock 40. The output of gate 60 isconnected to the input of another or third sealer 66. If, as in thepresent embodiment, it is desired to provide a specific wave form forthe output signal, the output of sealer 66 can be connected to the inputof a wave shaper such as the square wave generator or binarycountingflip-flop 68.

It will be apparent that, unless inhibiting terminal 62 of gate 60 isactivated, all of the pulses from clock 40 will appear in the gateoutput, and as divided by the divisor Z provided by third sealer 66 .(orby the product 22'. if one also considers the effect of flip-flop 68- inproviding a square-wave train from a pulse train) constitutes the fixedfrequency portion, for example P of the desired function.

Hence, (6) F F Z The desired time-variant frequency function is providedby the operation of the digital filter portion of the embodiment of FIG.3, and to this end means are provided for periodically resetting theoperation of the filter so that the desired function is repetitive orperiodic. For this purpose, either an automatic or manual control meanscan be provided, either being optional. FIG. 3 shows both control means,it being understood that use of the two reset means shown should bemutually exclusive and not conjunctive. The manual reset means simplycomprises switch means 70 for coupling as through single-legged gate 34,to an input of OR gate 36, a steady state DC level preferably of atleast the maganitude of pulses provided to gate 36 by AND gate 32.Alternatively, automatic reset means 86 can be provided in the formincluding static flip-flop 72 having its output. coupled, also asthrough gate 34, to OR gate 36. Flip-flop 72 is controlled at its setand reset inputs by respective coincidence gates 74 and 76. Gate 74 is atwo-input terminal gate having one input terminal 78 connected to theoutput of eompressor 48 and the other, or inhibiting terminal 80conneeted to the output of delay line 42. Similarly, gate 76 is atwo-input terminal gate having one input terminal 82 connected to theoutput of compressor 48, its other, or enable, terminal 84 beingconnected to the output of delay line 42.

In operation, it can be assumed that the automatic reset means isdisconnected, as by uncoupling the output of flip-flop 72 manual resetmeans is operative. Closure of switch 70 then introduces a steady-stateDC signal of appropriate magnitude from a suitable source (not shown.)such as a battery, Zener-controlled reference or the like, through gates34 and 36 to terminal 37 of gate 38.. Because terminal 37 is theenenergized at periodic enablement of gate 38 by clock pulses applied toterminal 39 will result in a series or train of pulses of. repetitionrate F being introduced into serial memory 42. The latter fills, in theperiodic of its delay time, until the first pulse of the train appearsat the memory output and thus, by virtue of feedback path 44, atrecirculating terminal 45 of gate 32.

Now, if the function to be produced is one wherein F is to vary from 1:3] kc. to F =3.3 kc. with variation of 2 from O to 0.5 second ashereinbefore suggested, one can assume that i is 1 megacycle, R -708 andT is 707 ,uSBC. Thus, because the clock pulses gate signal pulses intothe memory at a repetition rate of F after the first 707 pulses, the708th clock pulse and thus the first pulse out of memory 42 will occursimultaneously with a sampling pulse from compressor 48. Because thelatter pulse inhibits gate 32, no pulse reinsertion is made, assumingthat by that time switch 70 has been opened and no signal is applied togate 34. Hence, effectively a ZERO has been inserted into the pulsetrain (or string of ONES) in the delay line or memery. Obviously, withno energization of gate 34, the inhibition of each next 708th pulse willresult in a dumping of the memory linearly from a content of 707 pulsesto O pulses, and this will occur in a period which is the time constantof the 1 system, i.e.

hence T EOJ sec.

The repetition rate of the pulses in the output of memory 42 thus isseen to vary from a maximum of 1 megacycle to zero in 0.5 second. Asthese pulses pass through sealer 46, their frequency or repetition rateis divided by a number Y, such as 9, and thus inhibiting terminal 62 ofgate 60 is energized at a repetition rate which varies fromapproximately 111.1 kc. to zero. It will be apparent that at the maximuminhibiting action, every ninth clock pulse at terminal 64 is blocked,and at a minimum (i.e. zero inhibiting pulses) all clock pulses arepaassed through gate 60. The output gate 60 will thus vary during t to tfrom approximately 0.889 me. to l mc., as the output of first sealer or46 goes from 111.1 kc. to zero. If now second sealer 66 is provided sothat it divides input frequencies by a divisor Z of 135, and if staticflip-flop 68 is em ployed (and thus constitutes a divide-by-two device)then F will vary during t to tg 5 from 3292 c.p.s. to 3704 c.p.s. orapproximately 3.3 to 3.7 kc., thus providing the function sought. Thisis a repetitive function only if switch 70 is normally closed and openedperiodically. In order to assure an accurately timed periodic function,

automatic reset means 86 is preferably employed in place i of switch 70.In such case, flip-flop 72 is intended to provide the requisitesteady-state DC signal to gate 34 until memory 42 is filled. Thus, asthe first pulse along feedback path 44 appears at terminal 45simultaneously with the appearance at inhibit terminal 49 of thesampling pulse from compressor 42 (as hereinbefore described), thatfirst pulse and that sampling pulse also simultaneously appearrespectively at input terminals 84 and 82 of gate 76. This enables gate76 and the gate output. turns off from input terminal 52, and that onlythe a steady-state level, the

flip-flop 72, i.e. the output of the latter no longer energizes gate 34.Each sampling pulse thereaafter provided by compressor 48 will beaccompanied by a simultaneous signal pulse on path 44 until all of thepulses in memory 42 are dumped. The next sampling pulse appearing atterminal 82 will then not have an accompanying signal pulse at terminal48, and gate 76 is disabled and will have no output. The simultaneity ofpulses along feedback path 44 and from compressor 48 will have also keptgate 74 de-energized inasmuch as the pulses at terminal 80 act toinhibit the gate. Upon the appearance of the sampling pulse at terminal78 unaccompanied by a pulse at terminal 80, gate 74 becomes energized,turning flipfiop 72 on and delivering the requisite DC signal to gate 34to restart the process of filling the memory again. The interval betweenthe time at which the last pulse is discarded from the memory and thetime at which the memory becomes completely filled (illustrated in FIG.4 as the retrace time) is, of course, the time delay T of the memory.

The ramp-like function is then, as shown in FIG. 4, periodic with asweep-time of T between upper frequency limit F and lower limit F Itwill be seen that, in the embodiment of FIG. 3, the

parameters selected are related as follows:

Necessarily, the sampling period and the memory storage period cannot bethe same. Each must be an integral multiple of the clock period and themultiples must be relatively prime to each other. In the operation ofthe embodiment of FIG. 3, the frequency variation in the output ideallyvaries linearly but in small, discrete and uniform steps i-Af as shownin FIG. 5. This ideal can only be approached as the pulses within thedelay line approach uniform spacing therein.

A certain amount of FM noise will appear in the output as a function ofthe bunching, or non-uniform spacing, of the pulses circulating withinthe serial memory. In practice, the designer may minimize this problemthrough choice of the R :M ratio and/or by the use of two filters inseries, each similar to that of FIG. 3, but with the second having atotal time constant approaching the circulation time of the first.

With slight modification, other functions can readily be generated bythe device of FIG. 3. For example, first scaler 46 can be provided as acounter which responds to or counts only the ZEROS or lack of pulses inthe output of memory 4-2 (as by gating the clock pulses into the scaler46 in accordance with the inhibition of a gate by the output of thememory). In such case, the ramp of the output would be reversed and theFOUT of the example thus modified would vary downwardly instead ofupwardly.

By modifying the logic of the delay line input, the embodiment of FIG. 3can readily be made to generate a sawtooth type of function frequency,i.e. one exhibiting periodic alternating up and down ramps of frequencyvariation. Signals having linear functions of frequency of the typehereinbefore described, find application in precision measuringequipment, and in high resolution active sonar and radar devices.

Yet other functions of frequency can be generated with devices employingthe techniques of the present invention. For example, referring to FIG.6, there will be seen another embodiment of the present invention in ablock logic diagram of a generator for producing an exponentialfrequency function. This generator comprises AND gates 32 and 34buffered by OR gate 36, the latter being connected through gate 38 todelay line or memory 42 as 10 hereinbefore described. Also included areclock 40 for timing gate 38, and control apparatus, such as set-resetmeans 76, having its output connected to respective enabling inputterminals of gates 32 and 34.

The embodiment of FIG. 6 however includes two feedback paths, and 92.Path 90 connects the output of memory 42 to input terminal 45 of gate32. Path 92 connects the output of memory 42 to inhibiting terminal 94of two-input coincidence gate 96. The other input terminal 98 of gate 96is connected to the output of clock 40. The output of gate 96 isconnected to the input of scaler 48, the output of the latter being inturn connected to input terminal 100 of synchronizer means 102. Anotherinput terminal 104 of the synchronizer means is connected to feedbackpath 90. The output of the synchronizer means is coupled to inputterminal 50 of gate 34.

Lastly, the output of memory 42 is also connected through scaler 46 andwave-shaper 68 to provide a final output. Initially, it can be assumedthat memory 42 is completely empty. In operation, control means 70 thenprovides a steady-state DC of appropriate magnitude which enables bothgates 32 and 34. There being no inhibiting pulses at terminal 94, gate96 passes clock pulses at the repetition rate as generated by clock 40into scaler 48. The maximum pulsed output of the latter is, ashereinbefore described, F /R Assuming that the output of compressingscaler 48 is fed directly to terminal 50, bypassing synchronizer means102, all the scaled clock pulses are passed into enabled gate 34,through OR gate 36 and synchronously enabled gate 38 into memory 42. Itwill be apparent that the latter then begins to fill at an initiallyhigh rate with pulses spaced in time intervals of R times the clockpulse unit.

After T, has elapsed, the first pulse into the memory now appears in thefeedback paths.

The pulse output of the memory is fed back along path 99 and, as long asgate 32 is enabled, is wholly reinserted into the memory in-put.However, the memory output is also fed back along path 92. Each pulse onpath 92 inhibits gate 96, creating a corresponding ZERO or no-pulsecondition which appears in the pulse train output of gate 96. Scaler 48,counting the number of pulses from gate 96, thus provides aprogressively reduced pulse rate in its output as a result of theinhibiting effect of the feedback on gate 96.

In effect then, scaler 48 counts the ZEROS in the memory. Initially,when the memory is empty (full of ZEROS) and its frequency output istherefore zero, the output rate of scaler 48 is at its maximum. As thememory begins to fill and feedback commences, the output rate of scaler48 drops, reflecting the decreased number of ZEROS (or the increase innumber of pulses or ONES) in the memory.

Assuming no finite delays in the operation of gate 96 and scaler 48, itwill be seen that the output of gate 96, and thus scaler 48, is a pulseor ONE only when the memory output appearing at terminal 45 is ano-pulse or ZERO condition. Each ZERO appearing at terminal 45 then isaccompanied by a pulse at terminal 50 which is then inserted, in placeof the ZERO, into the memory. The addition of each newly inserted pulseto the reinserted pulses serves to increase the number of inhibitingsignals on gate 96. Finally, no ZEROS or no-pulse positions will be leftin the memory, and the latter will be filled with pulses spaced at timeintervals of l/F apart. If the clock frequency is l mc., then the memoryoutput frequency will have changed from zero to 1 me. in a finite time,the change being exponential. The provision of scaler 46 and wave-shaper68 merely provides a desired frequency reduction and does not affect thenature of the change itself.

As a practical matter, however, a finite delay will often occur in theoperation of the gates and sealers. As a result, to insure trulysynchronous operation, particularly simultaneity of ZEROS at terminal 45and ONES at terminal 50, the embodiment of FIG. 6 includes synchronizermeans 102. The latter can be formed as a flip-flop which is inhibited bypulses at terminal 104 so as to hold any pulse at terminal 100 until ano-pulse condition exists at terminal104, and thence to permittransmission of the held pulse from terminal 100 to terminal 50. Suchdevices are well known in the art.

Since certain changes may be made in the above apparatus withoutdeparting from the scope of the invention herein involved it is intendedthat all matter contained in the above description or shown in theaccompanying drawing shall be interpreted in an illustrative and not ina limiting sense. For example, the devices hereinbefore described can bemodified to count ONES instead of ZEROS (or vice-versa whereapplicable). This will usually result in a change in the sign of theoutput function. For instance, the device of FIG. 6 can be constructedso as to start with an initial condition wherein the delay line, insteadof being empty (all ZEROS) is completely full (all ONES), and feedbackafter scaling will inhibit ONES. The frequency output will then changeexponentially from an initial finite level to zero. Alternatively, thedevice of FIG. 6 can be constructed so as to start with an initialcondition wherein the delay line is empty except for at least oneinitial pulse, but gate 96 is inhibited by no pulses instead of pulses(or is pulse-enabled). In such event, the memory output is alsoexponential, but the rate of frequency change increases in time ratherthan decreases, to give a positive exponential instead of a negativeexponential.

Typically, the invention can be used to form other function generators.For example, if one feeds the output of the embodiment of FIG. 1 intoanother such embodiment, the output of the latter is a double integralof the initial input frequency.

What is claimed is:

1. A digital filter comprising:

means for serial-memory-time-compressing pulse samplings, taken at apredetermined rate, of only the frequency of an input signal; and

means for time-expanding the compressed pulse samplings so as to providean output signal having a frequency which is a weighted average, over apredetermined time period, of the input signal frequency.

2. A digital device adapted for filtering an input pulse train having achanging repetition rate, said device comprising:

means for taking periodic sampled data of only the repetition rate ofsaid input pulse train;

means having a serial storage device, with a feedback loop, for seriallytime-compressing said periodic sampled data; and

means for time expanding the compressed data so as to provide therefroman output pulse train having a repetition rate which is a function ofthe average magnitude of the repetition rate of said input pulse trainover a predetermined period of time.

3. A digital filter comprising:

means for converting an oscillatory signal into a pulse train having aninstantaneous repetition rate numerically equal to the instantaneousfrequency of said signal;

means for taking sampled data of only the repetition rate of said pulsetrain;

means for serially time-compressing said data; and

means for time-expanding the compressed data so as to provide a periodicsignal having a second repetition rate which is a weighted average, overa predetermined time period, of the repetition rate of said pulse train.

4, A digital filter comprising: means for time compressing in a serialmemory having a finite delay time digital sampling of only therepetition rate of an input signal said samplings being taken at apredetermined rate; means for frequency dividing said output of saidserial memory so as to provide an output pulse train wherein the numberand arrangement of pulses is a weighted average over a time period thatis the product of said delay time and said predetermined rate.

5. A digital filter comprising: means for providing a train of samplingpulses having a first repetition rate; first gating means responsive tosaid train for taking samplings of the repetition rate of a series ofinput pulses; serial memory means having an input connected to theoutput of said gating means for storing said samplings for apredetermined delay time period which is prime relative to the period ofsaid train; means for forming a feedback path from the output to theinput of said memory means, second gating means responsive to thecombination of a signal at the output of said memory means and a portionof said train for transmitting along said feedback path informationsignals selected in accordance with the nature of said combination;

means coupled to the output of said memory means for dividing therepetition rate of signals appearing at said output; and

means for synchronizing the operation of all of the preceding means.

6. A digital filter comprising:

means responsive to a train of periodic timing signals, having a firstrepetition rate, for providing sampling signals at a second rate whichis a sub-multiple of i said first rate, said sampling signals being ineither of two stable signal levels;

means for sampling the repetition rate of a periodic input signal inaccordance with said sampling signals and forming a sampled signal trainin which each sampled datum is the form of either of two stable signallevels;

means for storing seriatim said sampled signal train for a predeterminedtime interval which, in terms of the period of said timing signals isprime relative to the period of said sampling signals;

means for providing a feedback loop from the output to the input of thestorage means so that sampled data appearing at said output of thestorage means may be reinserted in its input;

means responsive to the level of one sampled datum in said feedback loopand to the level of a corresponding sampling signalfor enabling orinhibiting the reinsertion of said one datum into the input, of saidstorage means; and

means for dividing in accordance with a second submultiple therepetition rate of the seriatim data signals in the output of thestorage means.

7. A digital filter comprising:

a clock for generating periodic timing signals at a first repetitionrate;

means responsive to saidtiming signals for providing sampling signals ata second rate which is a submultiple of said first rate;

means for sampling the repetition rate of a periodic input signal inaccordance with said sampling signals;

means for storing seriatirn the sampling of said input signal for apredetermined time interval which ,in terms of the clock period is primerelative to the period of said sampling signals;

means for connecting a feedback loop from the output to the input of thestorage means responsively to one of the absence and the presence of asampling signal and for disconnecting said loop responsively to theother of said absence and presence of a sampling signal; and

means for dividing in accordance with a second submultiple therepetition rate of the seriatim samplings after said time interval, sothat the divided repetition 13 rate is a time-average of the repetitionrate of said input signal, which average is weighted according to theratio of said sub-multiples.

8. A digital filter comprising:

eans responsive to a digital clock for providing periodic Samplingsignals at a first rate which is a sub-multiple of the repetition rateof said clock;

gating means selectively enabled by said sampling signals for takingsamplings, at said first rate, of the frequency of an input signal;

serial memory means for storing said samplings for a delay time which interms of the clock period is relatively prime to the period of thesampling signals;

means for forming a feedback path from the output to the input of saidserial memory means;

gating means selectively inhibited by said sampling signals forpreventing transmission of signals through said feedback; and

means for dividing in accordance with said sub-multiple the repetitionrate of said samplings at the output of said memory means.

9. A digital filter comprising:

means for producing an input pulse train having an instantaneousrepetition rate which is a function of the instantaneous frequency of anoscillatory signal;

means responsive to a digital clock for providing periodic samplingpulses having a periodicity which is a multiple of a clock period;

gating means responsive to said sampling pulses for providing datapulses representative of the repetition rate of said pulse train;

means for storing said data pulses seriatim for a predetermined timeperiod which in terms of said clock period is prime relative to saidperiodicity of said sampling pulses;

means for forming a feedback path from the output to the input or" saidmeans for storing;

gating means responsive to said sampling pulses for disconnecting saidfeedback path; and

means for dividing the repetition rate of data pulses appearing at theoutput of said means for storing so as to provide an output pulse trainhaving a repetition rate which is a Weighted time-average of therepetition rate of said input pulse train.

10. A digital filter comprising:

a pulse generator for converting an oscillatory signal at its input intoan input pulse train at its output;

a digital clock for providing a clock signal at a first repetition rate;

first scaler means responsive to said clock signal for providingsampling pulses at a second rate which is a sub-multiple of said firstrate;

a first AND gate having an enabling input terminal connected to saidfirst sealer means, and another input terminal thereof connected to saidpulse generator;

a second AND gate having an inhibiting input terminal connected to saidfirst sealer means;

an OR gate for buffering together the outputs of said first and secondAND gates;

a third AND gate having an enabling input terminal connected to saiddigital clock and another input terminal connected to the output of saidOR gate;

a serial storage device having its input connected to the output of saidthird AND gate, and its output connected to another input terminal ofsaid second AND gate; and

second scaler means connected to the Output of said storage device fordividing the frequency of an output signal from said storage device inaccordance with said sub-multiple.

11. A digital filter comprising:

a clock for providing periodic timing signals at a first repetitionrate;

first scaler means for providing sampling pulses at a second repetitionrate, any period of which is an integral multiple of said first rate;

a first coincidence gate adapted to be enabled by said 5 sampling pulsesapplied to an input terminal thereof;

a second coincidence gate adapted to be inhibited by said samplingpulses applied to an input terminal thereof;

means for coupling an input pulse train to another input terminal of oneof said gates;

21 serial storage device having an input and an output between which apulse can transit in a finite time period which, in terms of the periodof said clock rate, is prime relative to the period of said second rate;

means for buffering together the outputs of said gates and forconnecting the buffered output, synchrnously with said clock, to theinput of said serial storage device;

means providing a feedback loop from the output of said storage deviceto another input terminal of the other of said gates; and

second sealer means connected to the output of said storage device fordividing the repetition rate of pulses at said output in accordance withsaid multiple.

12. A digital frequency function generator comprising:

means providing an input pulse train having, during a predetermined timeperiod, at least one change in repetition rate;

means for so-time-compressing, in a serial storage device having afeedback loop, said input pulse train as to provide a second pulse trainhaving a variable repetition rate which varies as a time-average of themagnitude of the repetition rate of said input pulse train over saidpredetermined time period; and

means responsive to said second pulse train for providing a third pulsetrain having a repetition rate which is a predetermined function of therepetition rate of said output pulse train.

13. A digital frequency function in g, in combination:

means for providing a first pulse train at a first repeti tion rate forestablishing timing increments;

first sealer means for providing a second pulse train at a secondrepetition rate which is -a sub-multiple of said first repetition rateand is synchronous therewith;

serial memory means having a storage time which in terms of saidincrements is prime relative to the period of said second pulse train;

means for providing a train of binary bits timed in accordance with saidfirst repetition rate and for storage in said memory means;

means providing a feedback loop from the output to the input of saidmemory means;

means for inhibiting feedback in said loop in accord ance with saidsecond repetition rate;

means for dividing the frequency of the output of bits from said memorymeans so as to provide a first output train;

means for summing said first output train with said first pulse train soas to provide a second output train; and

second sealer means for dividing the frequency of said second outputtrain.

14. A digital frequency function generator as defined in claim 13wherein said train of binary bits is predeterminedly limited in time andis periodically repeated. 70 15. A digital frequency function generator,comprising, in combination:

a clock providing at a first terminal a first pulse at a firstrepetition rate;

a first counter responsive to said first pulse train for providing asecond pulse train at a second repetition generator, compris- 1.5 ratewhich is a predetermined sub-multiple of said first rate;

a first coincidence gate having one input terminal adapted to inhibitsaid gate responsively to pulses of said second pulse train;

means providing a signal at a second terminal, a sec ond coincidencegate having a pair of input terminals, one being connected to saidsecond terminal and the output of said first gate, and the other beingconnected to said first terminal, said second gate being adapted toprovide an output when energized at both input terminals;

serial storage means having an input connected to the output of saidsecond gate and having an output terminal connected to the other inputterminal of said first gate;

a second counter responsive to the output of said storage means forproviding a third pulse train at a third repetition rate which is apredetermined sub-multiple of said first rate; and

a third coincidence gate having one input terminal adapted to inhibitsaid gate responsively to pulses of said third pulse train, and anotherinput terminal connected to said first terminal of said clock.

16. A digital frequency function generator as defined in claim whereinsaid means providing a signal at a second terminal comprises 'a bistabledevice having an output which is at one of two stable states accordingto the conditioning of a pair of input terminals, each of said terminalsbeing conditioned respectively according to the coincidence of thepulses in said second pulse train with one of the output of said storagemeans and the complement of the output.

17 A digital frequency function generator as defined in claim 15including a third counter responsive to the output of said thirdcoincidence gate for providing an output pulse train.

18. A digital frequency ing, in combination:

means for providing a clock pulse train at a first repetition rate forestablishing timing increments;

compressor means for providing a gating pulse train at a secondrepetition rate which is a sub-multiple of said first repetition rateand is synchronous therewith;

serial memory means having 'a storage time which in terms of saidincrements is prime relative to the period of said second pulse train;

means having an output for providing a train of binary bits timed inaccordance with one of said repetition rates connected to an input ofsaid memory means;

function generator, comprismeans providing at least one feedback loopfrom the output to the input of said memory means;

means for inhibiting one of the feedback in said loop and said secondrepetition rate by the other so as to alter the nature of said train ofbits;

means for dividing the frequency of the output of one type of bit insaid train of bits from said memory means so as to provide a firstoutput train;

means for summing said first output train with said first pulse train soas to provide a second output train;

means for scaling the frequency of said second output train, and

means operatively connected to said means having an output forperiodically providing said train of binary bits.

19. A digital frequency function generator comprising, in combination:

means for providing a tion rate;

first pulse train at a first repeti- -first scaler means for providing asecond pulse train at a second repetition rate which is a sub-multipleof said first repetition rate and is synchronous therewith;

serial memory means having a storage time which in terms of saidincrements is prime relative to the period of said second repetitionrate;

means providing a train of information bits initially spaced in time inaccordance with said second repetion rate and for storage in said memorymeans;

means providing a first feedback loop from the output to the input ofsaid memory means;

means providing a second feedback loop from the output to the input ofsaid memory means, and including said first scaler means and means forinhibiting said first sealer means so as to alter said second repetitionrate responsively to the bits appearing at the output of the memorymeans; and

means for scaling the output of said memory means.

References Cited UNITED STATES PATENTS 2,800,580 7/1957 Davies 340-3552,892,933 6/1959 Shaw 328-50 2,910,237 10/1959 Meyer 235-164 2,951,2028/1960 Gordon 32479 2,958,039 10/1960 Anderson 324-77 3,184,663 5/1965Mergler 318-39 MALCOLM A. MORRISON, Primary Examiner. K. MILDE, V.SIB-ER, Assistant Examiners.

1. A DIGITAL FILTER COMPRISING: MEANS FOR SERIAL-MEMORY-TIME-COMPRESSINGPULSE SAMPLINGS, TAKEN AT A PREDETERMINED RATE, OF ONLY THE FREQUENCY OFAN INPUT SIGNAL; AND MEANS FOR TIME-EXPANDING THE COMPRESSED PULSESAMPLINGS SO AS TO PROVIDE AN OUTPUT SIGNAL HAVING A FREQUENCY WHICH ISA WEIGHTED AVERAGE, OVER A PREDETERMINED TIME PERIOD, OF THE INPUTSIGNAL FREQUENCY.